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Synopsys outlines shift toward physics-based chip design modeling
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1 min readUpdated 2h ago
Drafted by AI, reviewed by the Ajako Taja Editorial Team · How we use AI

AI Summary

Synopsys is moving toward fundamental physics modeling to solve chip design errors at sub-nanometer scales, yet computational demands remain a high hurdle for industry adoption.

  • Chips and Cheese interviewed Synopsys engineering leads regarding the integration of fundamental physics into EDA tool flows.
  • Synopsys confirmed that modern chip design increasingly requires modeling at the sub-nanometer scale, where quantum effects significantly impact performance.
  • The transition from statistical modeling to first-principles physics remains a major industry hurdle that is still in its infancy.

Synopsys engineers recently detailed a strategy to incorporate deeper physical modeling into chip design workflows to account for quantum-level variables. This shift addresses the limitations of current statistical approximations, which struggle as transistors shrink toward atomic scales. However, the computational cost of simulating these physical interactions at scale remains a significant barrier for design teams. Whether this transition will become the new industry standard depends on if Synopsys can reduce the latency of these simulation tools to match existing production timelines.

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